Programmable logic devices such as field programmable gate arrays (FPGAs) allow a designer to avoid the expense of constructing an ASIC to implement a desired function. Rather than design an ASIC, a user may configure an off-the-shelf programmable logic device such as an FPGA to implement the desired function. An FPGA architecture is shown in FIG. 1. FPGA 100 includes a programmable fabric 105 that includes an array of programmable logic blocks 110 (also referred to in the art as programmable logic cells, configurable logic blocks, programmable logic elements, or programmable logic regions). Fabric 105 also includes a programmable interconnect 120 for programmably coupling signals into and out of logic blocks 110. Each logic block 110 includes one or more look-up tables (LUTs) that are configured by a user to implement a desired logical function. A characteristic of field programmable gate arrays is that logic blocks 110 are “fine-grain” logic blocks in that each logic block 110 may implement at best a few primitive logic functions. In other words, each logic block 110 may be configured to perform the functions of just a few logic gates. In contrast, other types of programmable logic devices such as complex programmable logic devices (CPLDs) have “coarse-grain” logic blocks that may be configured to perform the functions of many logic gates.
In general, a collection of fine-grain logic block such as logic blocks 110 may be used more efficiently to implement a user's design than would a comparable collection of coarse-grained logic blocks. Thus, FPGAs have become the dominant product in the programmable logic device industry. Despite their popularity, however, problems remain with respect to traditional FPGA design. For example, the fine-granularity of logic blocks 110 places great demands on routing structure 120 used to couple signals to and from logic blocks 110. Because each logic block 110 can implement just a few logic gates, a typical logical function that a user desires to implement requires the configuration of a fairly large number of logic blocks 110. Routing structure 120 must be quite complex to allow the necessary routing of signals from one logic block 110 to another across this number of logic blocks 110. Numerous junctions in routing structure 120 are thus configured with multiplexers or other switching structures to allow one conductor in routing structure 120 to couple to another conductor as desired. As a result, a configured routing structure 120 consumes a substantial amount of power, regardless of whether FPGA 100 is idle or operating.
Routing structure 120 is not the only power-hungry feature on FPGA 100. In addition, flip-flops or other storage devices (not illustrated) within each logic block 110 are clocked synchronously with each other. Routing a clock signal to each logic block 110 thus also consumes power, whether or not FPGA 100 is idle or actively performing logic. As clock rates are increased in modern FPGAs, this clock-based consumption of power is exacerbated. Indeed, it may be shown that nearly 90% of an FPGA's power consumption is attributable to the interconnect configuration and the clock distribution. Only about 5% of the total power budget is used within logic blocks 110 to perform the desired logical function. It will be appreciated, however, that the consumption of power by logic blocks 110 becomes more appreciable as transistor dimensions are pushed into the deep submicron region. Regardless of the component density, the standby or idle power consumption of an FPGA is substantial. As transistor dimensions are continually decreased, power dissipation increases.
Should an FPGA be powered from a line power supply, this idle power consumption is quite cheap to supply. However, in a handheld or mobile application, a conventional FPGA will demand too much power, limiting battery charge run time to unacceptably short periods. Thus, FPGAs have been provided with various sleep and standby modes to reduce idle power consumption. In a sleep mode, the programmable fabric is powered down such that it is unavailable to wake up the device. While it is common to use a configuration port command to place an FPGA into sleep mode (or into total power down), once the FPGA is in sleep mode the corresponding port logic may be non-functional such that a configuration port command is ineffective to exit a sleep or standby mode. For this reason, it is conventional for an FPGA to wakeup from the use of a dedicated wakeup input/output (I/O) pin. This is problematic, however, in that an FPGA has a limited number or I/O pins available for use. A dedicated wakeup pin is thus limiting the number of general purpose pins available on an FPGA. Accordingly, there is a need in the art for improved FPGA wakeup implementations.